Decreasing device size and increasing device density has traditionally been a high priority for the manufacturing of integrated circuits. Lithography has been the driving force for device scaling. Conventional optical lithography is limited to about 80 nm pitch for single exposure patterning. Whilst double and other multi-patterning processes can realize smaller pitch, these approaches are expensive and more complex.
Patterning of isolated features in a semiconductor device during fabrication may involve depositing a layer or layers over a substrate or other layer in or on which a feature is to be constructed, patterning the overlaying layer or layers to create regions through which the underlying substrate or other layer may be modified, modifying the underlying substrate or other layer in such regions, then removing some or all of the overlying layer or layers to reveal the modified underlying substrate or other layer. Optical lithography may be used for patterning the overlying layer or layers. For example, a hard mask may be deposited over the underlying substrate or layer, then a resist layer capable of being patterned by an optical lithography process deposited above the hard mask. Small features may then be patterned in the resist layer, such as through use of an optical lithography mask layered upon the resist layer, permitting subsequent modification of regions of the hard mask and, ultimately, underlying substrate or other layer, according to where the resist layer was patterned.
A difficulty arises when small features must be patterned in a resist in accordance with this or related procedures. Smaller features may have a greater variability in particular critical dimensions, from one feature to another or at different points within a feature, resulting in disadvantageous variability in semiconductor device structure. Such variability is greater for features that are patterned in relative geometric isolation with regard to other features. To ameliorate this problem, conventionally, non-printing lithographic assist features (SRAFs, Subresolution Assist Features) may be made during target feature processing. Assist features may be a multiplicity of features patterned into a resist or lithographic mask layer near a target isolated feature, but not subsequently etched or patterned into the underlying layer. Depositing such assist features in proximity to a target feature can improve the process window the target feature, rendering the target feature less isolated and thereby improving uniformity of geometry, without resulting in adding superfluous or unwanted features in the underlying substrate or other layer because such assist features are not subsequently pattered therein despite initially being patterned into the resist layer. Thus, these non-printing lithographic assist features help to improve the process window by reducing the sensitivity to lithographic process variations, such as variations of dose and focus. The size of these non-printing lithographic assist features is relatively small such that they do not print or transfer to the photoresist layer and otherwise produce unintended features in the integrated circuit. Unfortunately, the relatively small size of these non-printing lithographic assist features limits their benefit for improving the lithographic process window.
The process window for an isolated target feature is improved more with larger assist features than with smaller assist features. However, larger assist features may end up being patterned onto the underlying substrate or other layer, resulting in creation of superfluous unwanted features in addition to the intended target feature, offsetting the benefit larger assist features confer on the process window of a target feature. Thus, a method of improving the process window of target features during semiconductor manufacturing is needed